50473681
9781546776345
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
by Stuart Sutherland
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- Condition: New
- Provider: LightningBooks Contact
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- Condition: Like New
- Provider: Zebrasbooks Contact
- Provider Rating: 75%
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Product details
- ISBN-13: 9781546776345
- ISBN: 1546776346
- Edition: 1
- Publication Date: 2017
- Publisher: CreateSpace Independent Publishing Platform
AUTHOR
SUMMARY
Stuart Sutherland is the author of 'RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design', published 2017 under ISBN 9781546776345 and ISBN 1546776346.
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